timing-constraints
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
npx skills add a5c-ai/babysitter --skill timing-constraints --agent claude-code
Same command for any agent — swap --agent for codex, cursor, copilot.
Weekly change comes from our own snapshots, not the repository page — it measures attention, not adoption.
# Timing Constraints Skill Expert skill for FPGA timing constraint development following SDC (Synopsys Design Constraints) and Xilinx XDC standards. Provides deep expertise in clock definition, I/O timing, false paths, multicycle paths, and constraint validation. ## Overview The Timing Constraints skill enables comprehensive timing constraint development for FPGA designs, supporting: - Clock definition (create_clock, create_generated_clock) - Input/output delay constraints - False path identification and specification - Multicycle path constraints with setup/hold - Clock groups and relationships - Constraint coverage validation - Vendor-specific XDC extensions ## Capabilities ### 1. Primary Clock Definition Define primary clocks entering the FPGA: ```tcl # Primary clock on input pin create_clock -name sys_clk -period 10.000 [get_ports clk_100mhz] # Clock with duty cycle specification create_clock -name sys_clk -period 10.000 -waveform {0 5} [get_ports clk_100mhz] # Multiple primary clocks create_clock -name clk_a -period 8.000 [get_ports clk_125mhz] create_clock -name clk_b -period 6.667 [get_ports clk_150mhz] # Clock on GT/transceiver reference create_clock -name gt_refclk -period
- Overview
- Capabilities
- 1. Primary Clock Definition
- 2. Generated Clock Definition
- 3. Input Delay Constraints
- 4. Output Delay Constraints
- 5. False Path Constraints
- 6. Multicycle Path Constraints
- 7. Clock Groups
- 8. Max Delay for CDC
- 9. Physical Constraints (XDC Extensions)
- Process Integration
- Workflow
- 1. Clock Analysis
Output files generated:
What does the timing-constraints skill do?
Expert skill for developing and validating timing constraints. Writes SDC (Synopsys Design Constraints) and XDC files for FPGA timing closure.
How do I install it?
Run `npx skills add a5c-ai/babysitter --skill timing-constraints --agent claude-code` — it drops the skill into your project so the agent can pick it up. Swap the --agent value for codex, cursor or copilot if you use one of those.
Where does this skill come from?
From a5c-ai/babysitter, a repository with 1,642 stars. We read it straight from the repository tree rather than a submitted listing, so what you see here is what is actually published.
Is a popular skill a good skill?
Not necessarily. Stars measure attention, not adoption — a repository can trend for a week and be abandoned. That is why we show the weekly change from our own snapshots next to the total, instead of a single flattering number.