vhdl-language
Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.
npx skills add a5c-ai/babysitter --skill vhdl-language --agent claude-code
Same command for any agent — swap --agent for codex, cursor, copilot.
Weekly change comes from our own snapshots, not the repository page — it measures attention, not adoption.
# VHDL Language Skill Expert skill for VHDL (VHSIC Hardware Description Language) development following IEEE 1076 standards. Provides deep expertise in synthesizable VHDL code generation, coding guidelines, and best practices for FPGA design. ## Overview The VHDL Language skill enables comprehensive VHDL development for FPGA and ASIC designs, supporting: - IEEE 1076-2019 standard compliance - Synthesizable code generation - Entity, architecture, package, and component declarations - Synchronous process design with proper reset handling - Vendor-specific synthesis attributes - Testbench generation with assert statements - Detection and fix of common coding anti-patterns ## Capabilities ### 1. Entity and Architecture Definition Generate proper entity and architecture structures: ```vhdl -- Example: Parameterized FIFO Entity library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity sync_fifo is generic ( DATA_WIDTH : positive := 8; DEPTH : positive := 16; ALMOST_FULL_THRESHOLD : natural := 14; ALMOST_EMPTY_THRESHOLD : natural := 2 ); port ( clk : in std_logic; rst_n : in std_logic; -- Write interface wr_en : in std_logic; wr_data : in std_logic_vector(DATA_WIDTH-1 do
- Overview
- Capabilities
- 1. Entity and Architecture Definition
- 2. Synchronous Process Design
- 3. Package and Component Declarations
- 4. Vendor-Specific Synthesis Attributes
- 5. Numericstd Best Practices
- 6. Testbench Generation
- Process Integration
- Workflow
- 1. Analyze Requirements
- 2. Generate Module Structure
- 3. Validate Code
- Output Schema
Output files generated: Analyze with GHDL ghdl -a --std=08 src/module.vhd ghdl -a --std=08 tb/module_tb.vhd Run simulation ghdl -e --std=08 module_tb ghdl -r --std=08 module_tb --wave=wave.ghw Lint with Verible (if SystemVerilog) or vendor tools
What does the vhdl-language skill do?
Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.
How do I install it?
Run `npx skills add a5c-ai/babysitter --skill vhdl-language --agent claude-code` — it drops the skill into your project so the agent can pick it up. Swap the --agent value for codex, cursor or copilot if you use one of those.
Where does this skill come from?
From a5c-ai/babysitter, a repository with 1,642 stars. We read it straight from the repository tree rather than a submitted listing, so what you see here is what is actually published.
Is a popular skill a good skill?
Not necessarily. Stars measure attention, not adoption — a repository can trend for a week and be abandoned. That is why we show the weekly change from our own snapshots next to the total, instead of a single flattering number.