verilog-sv-language
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
Profile →npx skills add a5c-ai/babysitter --skill verilog-sv-language --agent claude-code
Same command for any agent — swap --agent for codex, cursor, copilot.
Weekly change comes from our own snapshots, not the repository page — it measures attention, not adoption.
# Verilog/SystemVerilog Language Skill Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices. ## Overview The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting: - IEEE 1800-2017 SystemVerilog standard - Verilog-2005 backward compatibility - Proper always_ff, always_comb, always_latch usage - SystemVerilog interfaces and modports - Parameterized modules with localparam - Packed and unpacked arrays - Packages and imports ## Capabilities ### 1. Proper Always Block Usage Use SystemVerilog always block variants correctly: ```systemverilog // Sequential logic - always_ff always_ff @(posedge clk or negedge rst_n) begin if (!rst_n) begin counter <= '0; state <= IDLE; end else begin counter <= counter + 1'b1; state <= next_state; end end // Combinational logic - always_comb always_comb begin // Default assignments prevent latches next_state = state; output_valid = 1'b0; case (state) IDLE: begin if (start) next_state = RUN; end RUN: begin output_valid = 1'b1; if (done) nex
- Overview
- Capabilities
- 1. Proper Always Block Usage
- 2. Parameterized Modules
- 3. SystemVerilog Interfaces
- 4. Packages and Imports
- 5. Packed and Unpacked Arrays
- 6. Blocking vs Non-Blocking Assignments
- 7. Synthesis Attributes
- Process Integration
- Output Schema
- Best Practices
- Always Block Selection
- Assignment Rules
What does the verilog-sv-language skill do?
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
How do I install it?
Run `npx skills add a5c-ai/babysitter --skill verilog-sv-language --agent claude-code` — it drops the skill into your project so the agent can pick it up. Swap the --agent value for codex, cursor or copilot if you use one of those.
Where does this skill come from?
From a5c-ai/babysitter, a repository with 1,642 stars. We read it straight from the repository tree rather than a submitted listing, so what you see here is what is actually published.
Is a popular skill a good skill?
Not necessarily. Stars measure attention, not adoption — a repository can trend for a week and be abandoned. That is why we show the weekly change from our own snapshots next to the total, instead of a single flattering number.